In recent years, with advancement of a processing technique, an SoC (System on a chip) obtained by mounting the entire system combining a large number of arithmetic circuits on one chip is realized. The large number of arithmetic circuits include a programmable core such as a processor. By combining programmable cores having different architectures depending on an application to be used, enhancement of arithmetic efficiency/resource use efficiency can be achieved. Such a method of implementing cores of different types is generally called heterogeneous multi-core.
A technique relating to the heterogeneous multi-core is disclosed in PTL 1. The technique disclosed in PTL 1 relates to a global compiler for a heterogeneous multi-core processor. In the technique disclosed in PTL 1, a heterogeneous multi-core processor system (HCMP) includes a plurality of different types of processor units (PU) and a shared memory. All the processor units can access to the shared memory.
In PTL 1, as architecture configuration information parameters, types and the number of PU's, an operation speed ratio of the PU with a bus, a type of a memory of each PU, a memory size, memory access latency, types of memories of the HCMP, size, latency, or the like are previously input. By utilizing such architecture configuration information parameters, it is possible to make the multiprocessor to operate efficiently.